GA-Assisted Standard Cell Extraction
by: Mengdi Zhu, Ronald Wilson, Reiner N. Dizon-Paradis, Olivia P. Dizon-Paradis, Domenic J. Forte, Damon L. Woodard
Description
Reverse Engineering (RE) of Integrated Circuits (ICs) involves studying an IC to comprehend its design, structure, and functionality. This process often entails identifying the key components within the design layout, frequently utilizing scanning electron microscope (SEM) images due to their high resolution, which offers detailed views of the IC’s layers. However, current approaches in IC RE generally assume access to a standard cell library for the transition from layout to netlist for functional verification, which is not always available. To overcome this limitation, we propose a golden-free automated pipeline for extracting the standard cell library from SEM layout images. Our method has achieved 100% detection rate on the AES design layout in both 90nm and 32nm technology nodes, compared to the golden reference, by relying solely on information from the contact layer. This finding highlights the potential of our approach to efficiently detect standard cells in complex layouts by focusing on the most relevant and distinctive features of the design.
Publications
Zhu, Mengdi; Wilson, Ronald; Dizon-Paradis, Reiner N.; Dizon-Paradis, Olivia P.; Forte, Domenic J.; Woodard, Damon L.
Genetic Algorithm-Assisted Golden-Free Standard Cell Library Extraction from SEM Images Conference Forthcoming
The 26th International Symposium on Quality Electronic Design (ISQED'25), Forthcoming.
@conference{Zhu2025Genetic,
title = {Genetic Algorithm-Assisted Golden-Free Standard Cell Library Extraction from SEM Images},
author = {Mengdi Zhu and Ronald Wilson and Reiner N. Dizon-Paradis and Olivia P. Dizon-Paradis and Domenic J. Forte and Damon L. Woodard},
year = {2025},
date = {2025-08-25},
booktitle = {The 26th International Symposium on Quality Electronic Design (ISQED'25)},
abstract = {Reverse Engineering (RE) of Integrated Circuits (ICs) involves studying an IC to comprehend its design, structure, and functionality. This process often entails identifying the key components within the design layout, frequently utilizing scanning electron microscope (SEM) images due to their high resolution, which offers detailed views of the IC's layers. However, current approaches in IC RE generally assume access to a standard cell library for the transition from layout to netlist for functional verification, which is not always available. To overcome this limitation, we propose a golden-free automated pipeline for extracting the standard cell library from SEM layout images. Our method has achieved 100% detection rate on the AES design layout in both 90nm and 32nm technology nodes, compared to the golden reference, by relying solely on information from the contact layer. This finding highlights the potential of our approach to efficiently detect standard cells in complex layouts by focusing on the most relevant and distinctive features of the design.},
keywords = {},
pubstate = {forthcoming},
tppubtype = {conference}
}